The invention relates to electronic communications, and more parrticularly to CDMA-based coding, transmission, and decoding/synthesis methods and circuitry.
Code division multiple access (CDMA) coding has been extensively used in such applications as cellular and satellite communications. CDMA signals increase the spectrum required for the transmission at a particular data rate by modulating each data symbol with a spreading code having a rate larger than the data rate. The same spreading code is used for each data symbol. Typically, the spreading code comprises of a few tens or a few hundreds of elements, called chips. To decrease the correlations among spreading codes assigned to different users, and thereby reduce the interference among different users, the data stream after spreading is typically scrambled with a pseudo-noise (PN) code that is generated serially and cyclically and has a larger period than the spreading code. Examples of such CDMA signal spreading are the schemes used by the IS-95/CDMA2000 and 3GPP systems.
With CDMA, the signals from all users simultaneously occupy the same frequency band, and the receiver separates the multiple signals by exploiting the crosscorrelation properties of the spreading and scrambling codes that are applied to each user's signal. The receiver attempts to match in time the spreading and scrambling codes of the desired signal with a replica of these codes. Only then the demodulation result is meaningful; otherwise it appears noise-like. Thus, if the arriving signals have different codes or different code offsets, they can be discriminated at the receiver. The CDMA code for each user is typically produced as the modulo-2 addition of a Walsh code with a pseudo-random code (two pseudo-random codes for QPSK modulation) to improve the noise-like nature of the resulting signal. A cellular system cell as illustrated in FIG. 1 could employ IS-95 or 3GPP for the air interface between the base station and the mobile user station.
The 3GPP system employs a 3.84 MHz bandwidth (a chip duration of 260 ns), and the spreading code length applied to each data symbol may vary from 4 chips to 256 chips. The number of chips per symbol is called the spreading factor (SF), and the SF stays constant during each 10 ms duration frame. However, the SF may change from frame to frame. Each frame is partitioned into 15 time slots (0.667 ms duration) with each time slot consisting of 2560 chips. Thus the number of data symbols per slot ranges from 10 to 640, and the number of data symbols per frame ranges from 150 to 9600.
In the 3GPP frequency division duplex (FDD) mode uplink, the Dedicated Physical Control Channel (DPCCH) is always spread by the code cc=Cch,256,0 with SF=256 while the Dedicated Physical Data Channel (DPDCH) is spread by the code cd,1=Cch,SF,k where k=SF/4 is the code number. Note that 3GPP uplink uses QPSK modulation with single-channel DPDCH and DPCCH being in phase and quadrature, respectively. The recursion defining even-numbered channel codes is concatenation: Cch,2n+1,2k=Cch,2n,k, Cch,2n,k with initial code Cch,4,1=“+1,+1,−1,−1”. Thus a consequence of the code selection k=SF/4 is that for two codes with SF's of length SF1 and SF2, where SF1<SF2, the part of the code for SF2 consisting of the first SF1 chips is identical to the code for SF1. In the uplink of 3GPP, the SF may take the values 2i, i=2,3,4,5,6,7,8. Because the code used for different SF's is a repetition of the code for SF=4, despreading for all possible SF's can be combined in a single process and as a result the number of despreaders need not increase.
The data rate and the SF used in each frame are specified by the Transport Format Control Indicator (TFCI) field that is transmitted in the DPCCH control channel. The DPCCH control channel consists of 15 time slots per frame, and the TFCI bits are time-multiplexed, together with other control information, among the 15 slots. The DPCCH control channel is always spread by the all-zero code (“+1,+1,+1, . . . +1,+1”) with SF=256 and can therefore be always despread once the received signal paths have been identified through a searching process at the receiver. By despreading the DPCCH control channel, at the end of a frame the receiver knows all of the TFCI symbols and can determine the data rate and the SF of the DPDCH data channel. Therefore, in order to despread the DPDCH data channel, the received data need to be stored for one entire frame period before despreading. Once the SF becomes known, the stored data need to be quickly transferred to the baseband part of the receiver to reduce the associated processing delay.
Thus the known method needs to store an entire frame prior to despreading and baseband processing; this requires large front-end memory, large data rate transfers between front-end memory and hardware and creates processing delay.